Design of 24 transistor static flipflop and differential cascode voltage switch

In this paper, I have designed a low-power circuit-shared static flip-flop (CS2FF) for low power digital VLSIs. The CS2FF consists of five static NORs and two inverters (INVs).The CS2FF utilizes a positive edge of a buffered clock signal, which is generated from a root clock, to take data into a master latch and a negative edge of the root clock to hold the data in a slave latch. The total number of transistors is only 24, which is the same as the conventional tri-state buffer based flipflop (TBFF) used in the most standard cell libraries. Spectre simulations in 0.18micrometer standard CMOS process demonstrated with different voltages that our proposed CS2FF achieved clock-to-Q delay of 17.4ns, setup time of 5.91ns, hold time of 1.17ns. The DCVS has been designed having less transistors. Cascode voltage switch logic (CVSL) refers to a CMOS-type logie family wich is designed for a certain advantages. It requires mainly N-channal Mosfet transistors to implement the logic using true and complementary input signals, and also needs two P-channel transistors at the top to pull one of the outputs high. This logic family is also known as Differential Cascode Voltage Switch Logic (DCVS or DCVSL).