Analysis and simulation of power consumption for sram

Static access memory (SRAM) is a building block of several logic circuits. SRAM is a fast memory which consumes low power. It is a fundamental building block of central processing unit of a computer. In this paper we design a low power circuit for 64 bit 5T SRAM using bottom-up approach. We use 0.12 micron meter technology and 90 neno meter technology for designing and simulation low power dissipation SRAM with dsch and micro wind. In this paper we simulate that reduction of power consumption in .12 micro technologies and 90 neno meter technology is 93% and 94% respectively.